The present disclosure relates generally to a semiconductor device and, more particularly, to a semiconductor device having a metal gate and a process of forming such a device using a gate replacement process.
As technology nodes shrink, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming a metal gate stack is termed a “gate last” process in which the final gate stack is fabricated “last,” which allows for a reduced number of subsequent processes, including high temperature processing that must be performed after formation of the gate. Benefits of a gate last scheme include suppression of growth of an interfacial layer underlying the gate dielectric which allows for a beneficial equivalent oxide thickness (EOT), a reduction of gate leakage, and a proper work function of a metal gate.
There are challenges to implementing such features and processes in semiconductor fabrication however. A “gate last” process uses a replacement gate methodology, which includes forming a dummy gate structure that is subsequently removed. A metal gate is formed in the opening created by the dummy gate structure's removal. However, with shrinking dimensions and the resulting increasing aspect ratios, filling the opening with conductive material may cause processing difficulties such as, adequate step coverage, voids, and/or other issues.